1. Field of the Invention
The present invention relates generally to reduced size field-effect transistor (FET) structures and to bipolar junction transistor (BJT) structures. More particularly, the present invention relates to reduced size FET with distributed gate feeds having tapered manifolds or junctions as well as BJTs having tapered manifolds or junctions
2. Description of Related Art
It is known in the art that high frequency FETs and BJTs, that are reduced in size and have distributed gate feeds, have certain characteristics. Reduced size FETs with distributed gate feeds are analogous to very small distributed amplifiers. As RF energy travels down the gate feed structure of the FET, the RF energy is attenuated and shifted in phase. An attenuation and phase shift means that there is a magnitude and a phase difference between the wave (field) entering the FET gate feed (manifold) and the wave field at the end of the FET gate feed (manifold). The attenuation and phase shift can degrade the combining performance of the FET structure at high frequencies. The attenuation and phase shift also limits a FET""s gain, power, and efficiency performance at high frequencies. The attenuation and phase shift also limits the upper operating frequency of the FET (or BJT)
What is needed is a reduced sized FET structure with distributed gate feeds that overcomes the high frequency performance and degradation limitations of FETs. What is also needed is an improved BJT structure that operates well in high power or high frequency situations.
The present invention provides reduced size field effect transistor (FET) and a reduced size bipolar junction transistor (BJT) that operate at high frequencies with improved performance and less degradation than previous FETs and BJTs. The present invention provides advantages that overcome previous problems related to reduced size FET structures with distributed gate feeds that have gain, power, efficiency and upper frequency performance limitations wherein the limitations are caused by attenuation along the distributed gate feed, and by phase differences along the input gate feed and along the output drain feed lines.
Embodiments of the present invention provide, a new reduced size FET gate feed structure which tapers both the gate feed line, also called a bar or manifold, and the attached gate finger widths (FET channel widths). The gate feed line is tapered with novel minor changes to reduce the FET size, layout and area. This novel gate feed structure efficiently compensates for attenuation and phase shift in the exemplary reduced size FET structure, improving the reduced sized FET""s maximum available gain performance by 1-2 dB at millimeter (mm) wave frequencies. The novel gate feed structure increases the upper operating frequency of the reduced size FET by up to 5 GHz, for instance, from 40 GHz to 45 GHz. Furthermore, the invention provides embodiments with other features and advantages in addition to or in lieu of those discussed above. Such features include, but are not limited to a tapered channel width, tapered source finger widths and tapered drain finger widths. Many of these features and advantages are apparent from the description below with reference to the following drawings